Synthesizing distributed buffer clock trees for high performance ASICs

An integrated design system is presented in this paper for synthesizing high performance clock distribution networks for application to high speed ASICs. An optimal clock skew schedule is determined which provides a set of localized non-zero clock skew values that improve both circuit performance and reliability. These clock skew values together with the functional hierarchy are used to design the topology of the clock distribution network and to determine the minimum clock path delays which satisfy the clock skew schedule. Distributed buffers targeted for CMOS technology are synthesized to emulate the delay values assigned to the individual branches of the clock tree. Maximum errors of less than 2.5% for the delay of the clock paths and 4% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated for an example circuit