DocumentCode :
3019499
Title :
A methodology for the verification of a “system on chip”
Author :
Geist, Daniel ; Biran, Giora ; Arons, Tamara ; Slavkin, Michael ; Nustov, Yvaenv ; Farkas, Monica ; Holtz, Karen ; Long, Andy ; King, Dave ; Barret, Steve
Author_Institution :
IBM Haifa Res. Lab., Israel
fYear :
1999
fDate :
1999
Firstpage :
574
Lastpage :
579
Abstract :
This paper summarizes the verification effort of a complex ASIC designated to be an “all in one” ISDN network router. This ASIC is unique because it actually consists of many independent components, called “cores” (including the processor). The integration of these components onto one chip results in an ISOC (Integrated System On a Chip). The complexity of verifying an ISOC is virtually impossible without a proper methodology. This paper presents the methodology developed for verifying the router. In particular, the verification method as well as the tools that were built to execute this method are presented. Finally, a summary of the verification results is given
Keywords :
ISDN; application specific integrated circuits; automatic testing; circuit simulation; computer debugging; computer testing; formal verification; integrated circuit testing; microprocessor chips; telecommunication computing; telecommunication equipment testing; telecommunication network routing; ISDN network router; complex ASIC; system-on-chip; verification methodology; Application specific integrated circuits; Chip scale packaging; Debugging; Fabrication; Hardware; Permission; Protocols; Silicon; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1999. Proceedings. 36th
Conference_Location :
New Orleans, LA
Print_ISBN :
1-58113-092-9
Type :
conf
DOI :
10.1109/DAC.1999.781380
Filename :
781380
Link To Document :
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