Gain stage design based on narrow-width methodology in SOI technology

Author

Cheung, Denny T Y ; Lau, Jack ; Chan, Philip C.H.

Author_Institution

Dept. of EEE., Hong Kong Univ. of Sci. & Technol., Hong Kong

Volume

1

fYear

1996

fDate

12-15 May 1996

Firstpage

219

Abstract

An optimized gain stage design strategy for operational amplifiers in 2 μm SOI technology is described. This approach is known as Narrow-Width Methodology (NWM), which offers a parasitic capacitance reduction in the significant node as compared with bulk technology because of the isolated mesa used in SOI technology. Therefore, when a two-stage Miller compensated op amp is designed, a smaller Miller compensation capacitance (C_c) is employed to ensure stability. Moreover, the performance of unity-gain frequency (f_unity) is improved. Simulation results show that, when NWM is implemented in the output transistor, f_unity can be achieved up to 180 MHz with C_c=0.045 pF in SOI technology, while f_unity equals 84 MHz with C_c=0.095 pF in bulk counterparts

Keywords

analogue integrated circuits; capacitance; circuit stability; compensation; frequency response; integrated circuit design; linear network synthesis; operational amplifiers; silicon-on-insulator; 0.045 pF; 180 MHz; 2 micron; Miller compensation capacitance; SOI technology; Si; isolated mesa; narrow-width methodology; operational amplifier; optimized gain stage design strategy; parasitic capacitance reduction; stability; two-stage Miller compensated op amp; unity-gain frequency; Circuit simulation; Design optimization; Equations; Isolation technology; Lifting equipment; Operational amplifiers; Parasitic capacitance; SPICE; Silicon; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-3073-0

Type

conf

DOI

10.1109/ISCAS.1996.539868

Filename

539868