Title :
A CMOS digitally programmable current multiplier
Author :
Paulino, N. ; Franca, J.E.
Author_Institution :
Inst. Superior Tecnico, Lisbon, Portugal
Abstract :
This paper describes the design and test of a CMOS digitally programmable current multiplier which multiplies an input current by a digital gain varying from 0 to 255/256. The current multiplier is realised using binary weighted regulated cascode current mirrors implemented in a two-stage segmented architecture to reduce the circuit area. The resulting harmonic distortion is better than 67 dB, and the power dissipation is 2.38 mW for an input current of 200 μA at 5 V supply
Keywords :
CMOS analogue integrated circuits; analogue multipliers; integrated circuit design; 2.38 mW; 200 muA; 5 V; CMOS multiplier; binary weighted regulated mirrors; cascode current mirrors; digitally programmable current multiplier; harmonic distortion; power dissipation; two-stage segmented architecture; CMOS digital integrated circuits; CMOS integrated circuits; CMOS technology; Circuit testing; Diodes; Integrated circuit testing; Mirrors; Noise level; System testing; Voltage;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.539877
