Datapath cell design strategy for channelless routing

In many advanced microprocessors, including all recent Intel microprocessors, the datapath is implemented in a bit-sliced structure, in which data inputs and control signals are arranged orthogonally. As of today, physical layout of such datapaths is performed manually, and has been shown to be a major productivity bottleneck in many recent designs. In this paper, a methodology is presented for layout generation of such bit-sliced structures using library cells. Special techniques are proposed for layout planning and connectivity of library cells to meet the high density requirements of datapath design. Experiments on real examples have shown very promising results. Significant improvements have been achieved over conventional approaches