DocumentCode
3019701
Title
Design of a multistage decimation-interpolation filter
Author
Hansen, Vic
Author_Institution
Tektronix, Inc., Beaverton, OR
Volume
12
fYear
1987
fDate
31868
Firstpage
900
Lastpage
903
Abstract
A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.
Keywords
Band pass filters; Control systems; Convolution; Digital filters; Filtering; Finite impulse response filter; Frequency; Hardware; Interpolation; Passband;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '87.
Type
conf
DOI
10.1109/ICASSP.1987.1169830
Filename
1169830
Link To Document