A mixed asymmetric/symmetric (MASS) MOSFET cell for ASICs

Author

Kumagai, Kouichi ; Kurosawa, Susumu ; Iwaki, Hiroaki ; Hamatake, Nobuhisa ; Yoshino, Akira ; Okumura, Koichiro ; Ohuchi, Kugao ; Nakajima, Kazuhiro ; Asahina, Akihiro ; Yamazaki, Yoshiyuki

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1994

fDate

19-23 Sep 1994

Firstpage

116

Lastpage

119

Abstract

A new basic cell for ASICs which embeds fixed asymmetric and symmetric (MASS) LDD MOSFETs is proposed. A 142 KG MASS cell SOG has been developed using a half micron CMOS technology with two extra masks. The MASS cell has no area penalty for static latch and flip-flop block layout, and it has 13% drivability improvement without high cost and fine process technology. The advantages of the MASS cell application to ASICs have been confirmed

Keywords

CMOS logic circuits; application specific integrated circuits; cellular arrays; flip-flops; integrated circuit layout; logic arrays; 0.5 micron; ASIC; LDD MOSFETs; SOG; flip-flop block layout; half micron CMOS technology; mixed asymmetric/symmetric MOSFET cell; sea-of-gates; static latch block layout; Application specific integrated circuits; CMOS technology; Flip-flops; Hot carriers; Ion implantation; Laboratories; Large scale integration; Latches; MOSFET circuits; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404596

Filename

404596