Title :
A 200 ps 0.5 μm CMOS gate array family with high speed modules
Author :
Nishio, Yoji ; Hara, Hideo ; Iwamura, Masahiro ; Kaminaga, Yasuo ; Koike, Katsunori ; Hirose, Kosaku ; Noto, Takayuki ; Oguchi, Satoshi ; Yamamoto, Yoshihiko ; Ono, Takeshi
Author_Institution :
Hitachi Res. Lab., Ibaraki, Japan
Abstract :
A 0.5 μm CMOS gate array family with high speed modules is discussed. Measured access time of the 8 Kbit 2-port metallized RAM is 6.3 ns. Simulated access time of the 16 Kbit diffused RAM is 5.5 ns. Propagation delay time of the 2-input NAND is 200 ps at a standard load. Use of high performance internal logic circuits, high speed compiled RAM, improved GTL (Gunning Transceiver Logic), and PLL (Phase Locked Loop) realizes operation of over 100 MHz at 3.3 V. This 3F (Flexible, Fast, and Friendly) ASIC family can be applied to high speed processors in workstations and graphics equipment
Keywords :
CMOS logic circuits; CMOS memory circuits; NAND circuits; application specific integrated circuits; cellular arrays; logic arrays; random-access storage; 0.5 micron; 100 MHz; 16 Kbit; 2-input NAND; 2-port metallized RAM; 200 ps; 3.3 V; 5.5 ns; 6.3 ns; 8 Kbit; ASIC family; CMOS gate array family; GTL; Gunning Transceiver Logic; PLL; diffused RAM; high speed compiled RAM; high speed modules; phase locked loop; Application specific integrated circuits; Circuit simulation; Graphics; Logic circuits; Metallization; Phase locked loops; Propagation delay; Time measurement; Transceivers; Workstations;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404597
