CAD issues for CMOS VLSI design in SOI

Author

Shepard, Kenneth L.

Author_Institution

Integrated Syst. Lab., Columbia Univ., New York, NY, USA

fYear

2001

fDate

2001

Firstpage

105

Lastpage

110

Abstract

This paper reviews recent progress in making circuit-level CAD tools for the design of digital integrated circuits SOI-aware, specifically transistor-level static timing and static noise analysis tools. This involves abstracting the SOI device physics of the floating body, allowing estimates of the body voltage variation under various switching activity assumptions. These body voltage estimates are then applied as “initial conditions” in the constituent simulations of the static analyses. Results are presented for a prototype static timing analysis tool and a commercial static noise analysis tool

Keywords

CMOS digital integrated circuits; VLSI; circuit CAD; circuit analysis computing; integrated circuit design; integrated circuit noise; silicon-on-insulator; timing; CAD issues; CMOS VLSI design; SOI device physics; SOI-aware tools; Si; body voltage estimation; body voltage variation; circuit-level CAD tools; digital PD-SOI circuits; digital integrated circuits; static noise analysis tool; static timing analysis tool; switching activity assumptions; transistor-level tools; Analytical models; Circuit simulation; Design automation; Digital integrated circuits; Integrated circuit noise; Physics; Prototypes; Timing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2001 International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1025-6

Type

conf

DOI

10.1109/ISQED.2001.915213

Filename

915213