• DocumentCode
    3020248
  • Title

    Design and Implementation of an Efficient Stack Machine

  • Author

    Schoeberl, Martin

  • Author_Institution
    JOP Design, Vienna, Austria
  • fYear
    2005
  • fDate
    04-08 April 2005
  • Abstract
    Although virtually every processor today uses a loadstore register architecture, stack architectures attract attention again due to the success of Java. The intermediate language of Java, the Java bytecodes, is stack based and therefore a hardware realization of the Java Virtual Machine (JVM), a Java processor, is also stack based. In this paper two different architectures, found in Java processors, are presented. Detailed analysis of the JVM access patterns to the stack prove that a simpler and faster solution is possible. The proposed solution is a stack with two levels of on-chip cache.
  • Keywords
    Java; cache storage; computer architecture; data structures; system-on-chip; virtual machines; Java bytecodes; Java processor; Java virtual machine; load-store register architecture; on-chip cache; stack architecture; stack machine; Application software; Computer architecture; Computer languages; Distributed processing; Hardware; Java; Pattern analysis; Registers; Virtual machining;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
  • Print_ISBN
    0-7695-2312-9
  • Type

    conf

  • DOI
    10.1109/IPDPS.2005.161
  • Filename
    1420020