• DocumentCode
    3020251
  • Title

    Atomic scale simulation of a junctionless silicon nanowire transistor

  • Author

    Ansari, Lida ; Feldman, Baruch ; Fagas, Giorgos ; Colinge, Jean-Pierre ; Greer, James C.

  • Author_Institution
    Tyndall Nat. Inst., Univ. Coll. Cork, Cork, Ireland
  • fYear
    2011
  • fDate
    14-16 March 2011
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
  • Keywords
    MOSFET; density functional theory; elemental semiconductors; nanowires; semiconductor quantum wires; silicon; Si; atomic scale simulation; bulk adatom; density functional theory; gate voltage; junctionless silicon nanowire transistor; size 3 nm; source-drain bias; surface adatom; Doping; Electrostatics; Logic gates; Photonic band gap; Silicon; Transistors; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on
  • Conference_Location
    Cork
  • Print_ISBN
    978-1-4577-0090-3
  • Electronic_ISBN
    978-1-4577-0089-7
  • Type

    conf

  • DOI
    10.1109/ULIS.2011.5757980
  • Filename
    5757980
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3020251