Title :
Characterization and modeling of capacitances in FD-SOI devices
Author :
Ben Akkez, I. ; Cros, A. ; Fenouillet-Beranger, C. ; Perreau, P. ; Margain, A. ; Boeuf, F. ; Balestra, F. ; Ghibaudo, G.
Author_Institution :
IMEP-LAHC, INP Grenoble, Grenoble, France
Abstract :
Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and Box capacitances in the structure.
Keywords :
MOSFET; capacitance; numerical analysis; semiconductor device models; silicon-on-insulator; 2D numerical simulation; FD-SOI MOS devices; FD-SOI devices; gate lengths; gate-to-channel capacitance; parasitic capacitances;
Conference_Titel :
Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on
Conference_Location :
Cork
Print_ISBN :
978-1-4577-0090-3
Electronic_ISBN :
978-1-4577-0089-7
DOI :
10.1109/ULIS.2011.5757984
