Physically-based, multi-architecture, analytical model for junctionless transistors

In this paper we propose a new physically-based analytical model for junctionless transistors. Various MOSFET architectures based on single-gate (SG), double-gate (DG) and Gate-All-Around (GAA) transistors are studied. In particular the trade-off between the electrostatic control and the current drivability (first-order evaluation) is evaluated. Comparisons between numerical and analytical results are done in order to verify assumptions for pinch-off voltage and depletion regions. Traditional analytical expressions for this phenomenon are re-explored, and used to derive some technological guidelines.