• DocumentCode
    3020487
  • Title

    Revisited approach for the characterization of Gate Induced Drain Leakage

  • Author

    Rafhay, Quentin ; Xu, Cuiqin ; Batude, Perrine ; Mouis, Mireille ; Vinet, Maud ; Ghibaudo, Gérard

  • Author_Institution
    IMEP-LAHC, Grenoble, France
  • fYear
    2011
  • fDate
    14-16 March 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This work presents a re-investigation of the electrical characterisation of Gate Induced Drain Leakage (GIDL) [1][2]. The limits of the previously proposed extraction methods are underlined and a new approach is introduced. This new approach enables a better extraction of the GIDL parameters compared to the conventional methods, provided that a new step of electric field extraction is used. Finally, the experimental application of this new approach confirms its ability to quantify the impact of trap assisted tunnelling on GIDL.
  • Keywords
    MOSFET; leakage currents; semiconductor device breakdown; electric field extraction; gate induced drain leakage; Electric fields; Equations; Logic gates; Mathematical model; Solids; Temperature measurement; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on
  • Conference_Location
    Cork
  • Print_ISBN
    978-1-4577-0090-3
  • Electronic_ISBN
    978-1-4577-0089-7
  • Type

    conf

  • DOI
    10.1109/ULIS.2011.5757994
  • Filename
    5757994