A VLSI architecture for the K-best Sphere-Decoder in MIMO systems

Author

Cervantes-Lozano, Pedro ; Gonzalez-Perez, Luis F. ; Garcia-Garcia, Andres D.

Author_Institution

ITESM Campus Estado de Mexico, Atizapán de Zaragoza, Mexico

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

1

Lastpage

6

Abstract

This article presents a VLSI architecture for the K-best Sphere-Decoder (K-best SD) algorithm as a hard-output detector in the context of SM-MIMO (Spatial Multiplexing Multiple-Input Multiple-Output) systems immersed in Rayleigh fading channels. The design and implementation of its corresponding data-path and control-path components over FPGA devices are considered. Results on synthesis, bit error rate performance, and data throughput are reported.

Keywords

MIMO communication; Rayleigh channels; VLSI; decoding; error statistics; field programmable gate arrays; space division multiplexing; FPGA devices; K-best SD algorithm; K-best sphere-decoder algorithm; MIMO systems; Rayleigh fading channels; SM-MIMO systems; VLSI architecture; bit error rate performance; control path components; data path components; data throughput; hard-output detector; spatial multiplexing multiple-input multiple-output systems; Bit error rate; Complexity theory; Computer architecture; Fading; MIMO; Signal processing algorithms; Vectors; K-best Sphere-Decoder; MIMO systems; Rayleigh fading channels; VLSI architectures; hard-output detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4673-2919-4

Type

conf

DOI

10.1109/ReConFig.2012.6416791

Filename

6416791