A reference low-complexity structured ASIC

Structured ASICs are designed to bridge the gap between ASICs and FPGAs in terms of cost and performance. By predefining most of the manufacturing masks they highly reduce time-to-market (TTM), non-recoverable engineering (NRE) costs and lithography hazards while exhibiting higher performances than FPGAs thanks to hardwired configuration and interconnections. Many structured ASICs architectures aiming at achieving high performances have been proposed, their delay, power consumption and area have been evaluated and compared to standard cells implementations. However, the evaluation of their cost in terms of dedicated software development, full custom design, cells libraries development and comparison with structured ASICs using the same process is seldom investigated. In this paper, we present a structured ASIC which minimizes full-custom design complexity, technology migration cost and ensures compatibility with an unmodified industrial design flow. We evaluate its performance in a 65 nm process and compare it to standard cells and FPGA implementations. Our goal with this “simple” structured ASIC is to provide a reference which allows to evaluate if performance gains due to design enhancements outweigh higher complexity and costs.