Source/drain engineered ultra low power analog/RF UTBB MOSFETs

We present a novel optimization technique for ultra-low-power analog/RF Ultra Thin Body BOX (UTBB) MOSFETs. UTBB devices are optimized in bias range corresponding to peak of transconductance-to-current ratio (g_m/I_ds) and cut-off frequency (f_T) product i.e. g_mf_T/I_ds as it represents a “sweet spot” between speed and power. It is demonstrated that the use of underlap source/drain (S/D) architecture in UTBB devices improve g_mf_T/I_ds, intrinsic voltage gain (A_VO), cut-off frequency (f_T) and linearity (VIP₃) with downscaling.