IP Lookup on a Platform FPGA: A Comparative Study

The efficient use of present resources is an important challenge in the design of embedded systems based on a platform FPGA. This paper discusses algorithms for IP lookup focusing on comparability and tradeoffs, rather than maximum performance. A hashing-based algorithm and a tree-based algorithm as examples for the two most common classes of IP lookup approches are investigated with regard to their implementation in programmable logic, their resource use and their performance, measured in lookup time. Through simulations it is determined how performance varies with changed resource availabity. A comparison also takes into account processor-based approaches and discusses use cases for the different implementations.