Title :
Test pattern generators for distributed and embedded built-in self-test at register transfer level
Author :
Vorisek, Vladimir
Author_Institution :
Inst. of Inf., Slovak Acad. of Sci., Bratislava, Slovakia
Abstract :
The poster presents Ph.D. thesis in the area of test pattern generators (TPGs) for application in distributed and embedded Built-In Self-Test (BIST). The goal of this work is to develop a general scheme of designing built-in TPGs for basic arithmetic elements such as adders, subtracters, multiplexers, comparators at register transfer level (RTL) of circuit description
Keywords :
automatic test pattern generation; built-in self test; integrated circuit testing; RTL circuit; adder; arithmetic element; built-in self-test; comparator; distributed BIST; embedded BIST; multiplexer; register transfer level; subtracter; test pattern generator; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Multiplexing; Registers; Test pattern generators;
Conference_Titel :
Quality Electronic Design, 2001 International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1025-6
DOI :
10.1109/ISQED.2001.915236
