Title :
Experiences with Soft-Core Processor Design
Author :
Plavec, Franjo ; Fort, Blair ; Vranesic, Zvonko G. ; Brown, Stephen D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application. This paper describes the UT Nios implementation of Altera´s Nios architecture. A benchmark set appropriate for soft-core processors is defined. Using the benchmark set, the performance of UT Nios is explored and compared with the commercial implementation.
Keywords :
field programmable gate arrays; instruction sets; logic design; reduced instruction set computing; FPGAs; Nios architecture; UT Nios implementation; benchmark set; field programmable gate arrays; soft-core processor design; Application software; Computer architecture; Field programmable gate arrays; Hardware design languages; Logic circuits; Manufacturing processes; Microprocessors; Process design; Programmable logic arrays; Reduced instruction set computing;
Conference_Titel :
Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
Print_ISBN :
0-7695-2312-9
DOI :
10.1109/IPDPS.2005.209
