Low-power reconfigurable VLSI architecture for the implementation of FIR filters

This paper presents a custom reconfigurable VLSI architecture that is tailored for the implementation of low-power, medium/high order, digital finite impulse response (FIR) filters. These are realized within a reconfigurable array that consists of heterogeneous, programmable, arithmetic-logic units. The reconfigurable design is based on the primitive operator design (POF) technique. The concept of a genetic algorithm (GA) is introduced, which utilizes a randix-4, 256-point fast-Fourier-transform (FFT) to calculate the frequency response of the evolved filters. The results related to the performance, physical-area and power consumption make this architecture very competitive in comparison with other industrial, general purpose FPGAs.