DocumentCode :
3020821
Title :
Low power via reduced switching activity and its application to PLAs
Author :
Hossain, Razak ; Albicki, Alexander
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear :
1994
fDate :
19-23 Sep 1994
Firstpage :
100
Lastpage :
103
Abstract :
In this paper a systematic study of the expected switching activity (ESA) in combinational logic circuits is presented. Based on this study, a technique for reducing the power dissipation in two-level combinational logic is presented. The paper also discusses the switching activity in multilevel circuits
Keywords :
combinational circuits; combinational switching; logic design; multivalued logic circuits; programmable logic arrays; PLA; combinational logic circuits; multilevel circuits; power dissipation reduction; switching activity reduction; CMOS logic circuits; CMOS technology; Combinational circuits; Digital circuits; Electromigration; Logic circuits; Logic gates; Power dissipation; Programmable logic arrays; Switching circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
Type :
conf
DOI :
10.1109/ASIC.1994.404600
Filename :
404600
Link To Document :
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