DocumentCode
3020823
Title
Embedded MPLS Architecture
Author
Peterkin, Raymond ; Ionescu, Dan
Author_Institution
Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada
fYear
2005
fDate
04-08 April 2005
Abstract
This paper presents a hardware architecture for Multi Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utilization. Furthermore it increases the performance of internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based. MPLS performance can be enhanced by executing core tasks (i.e. label stack modification) in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware/software design of MPLS on an FPGA for increased performance and efficiency. Greatest emphasis is placed on the hardware components.
Keywords
Internet; embedded systems; field programmable gate arrays; hardware-software codesign; multiprotocol label switching; reconfigurable architectures; telecommunication traffic; FPGA; Internet traffic; embedded MPLS architecture; hardware-software design; multiprotocol label switching; Application software; Bandwidth; Computer architecture; Degradation; Hardware; Internet; Multiprotocol label switching; Protocols; Software design; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International
Print_ISBN
0-7695-2312-9
Type
conf
DOI
10.1109/IPDPS.2005.195
Filename
1420041
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