Submicron BiCMOS technologies for supercomputer and high speed system implementation

Author

Bastani, B. ; Biswal, M. ; Iranmanesh, A. ; Lage, C. ; Bouknight, L. ; Ilderem, V. ; Solheim, A. ; Burger, W. ; Lahri, R. ; Small, J.

Author_Institution

Nat. Semicond., Puyallup, WA, USA

fYear

1990

fDate

17-19 Sep 1990

Firstpage

7

Lastpage

10

Abstract

Submicron process technologies that allow a full implementation of CPU, first-level cache, second-level cache, and the main memory in the BiCMOS approach are described. CPU standard cells up to 100 K ECL gate density with embedded CMOS and BiCMOS SRAM, X9 cache memories, and 1-Meg ECL I/O SRAMs with less than 7-ns access time have been achieved

Keywords

BIMOS integrated circuits; integrated circuit technology; integrated memory circuits; 7 ns; BiCMOS; BiCMOS SRAM; CPU standard cells; ECL I/O SRAMs; ECL gate density; X9 cache memories; access time; embedded CMOS; first-level cache; high speed system; main memory; second-level cache; submicron process technologies; supercomputer; Application specific integrated circuits; BiCMOS integrated circuits; CMOS process; CMOS technology; Cache memory; Costs; Random access memory; Resistors; Semiconductor device manufacture; Supercomputers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130145

Filename

130145