Energy efficient signaling in deep submicron CMOS technology

Author

Dhaou, Imed Ben ; Sundararajan, Vijay ; Tenhunen, Hannu ; Parhi, Keshab K.

Author_Institution

Dept. of Electron., R. Inst. of Technol., Stockholm, Sweden

fYear

2001

fDate

2001

Firstpage

319

Lastpage

324

Abstract

In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeater insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeater insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 μm, 2.5 V, 6-metal-layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5 V down to 1.5 K

Keywords

CMOS integrated circuits; ULSI; integrated circuit interconnections; low-power electronics; repeaters; 0.25 micron; 1.5 V; 2.5 V; 6-metal-layers CMOS process; VIJIM; deep submicron CMOS technology; energy efficient signaling; heuristic algorithm; low-voltage signaling; on-chip interconnect; repeater insertion; robust inverter chain; supply voltage; Algorithm design and analysis; CMOS technology; Delay; Energy efficiency; Heuristic algorithms; Inverters; Noise robustness; Repeaters; Signal design; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2001 International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1025-6

Type

conf

DOI

10.1109/ISQED.2001.915250

Filename

915250