Title :
Performance improvement for high speed devices using E-tests and the SPICE model
Author :
Kwon, Tae-Jin ; Lee, Sang-Hoon ; Kim, Tae-Seon ; Lee, Hoe-Jin ; Park, Young-Kwan ; Kim, Taek-Soo ; Kim, Seok-Jin ; Kong, Jeong-Taek
Author_Institution :
Semicond. R&D Div., Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
In order to improve the chip performance, a design or a process optimization occurs occasionally at the manufacturing stage. However modifying the design and the process through the real wafer processing of fabrication increases the time to market. This paper describes an efficient simulation approach for a new IC process centering method based on the SPICE model and E-tests (i.e., threshold voltage and saturation current). This methodology enables obtaining the optimal E-tests for improving the performance of high speed devices, before changing the real process conditions. In addition, the Response Surface Method (RSM) is used as a significant statistical tool for this new procedure. The validity and efficiency of this approach are proven by applying it to an IC process design centering problem for ALPHA CPU
Keywords :
SPICE; circuit optimisation; circuit simulation; high-speed integrated circuits; integrated circuit modelling; integrated circuit testing; microprocessor chips; statistical analysis; surface fitting; ALPHA CPU; E-tests; IC process centering method; SPICE model; design centering problem; high speed devices; process optimization; real process conditions; real wafer processing; response surface method; saturation current; simulation approach; statistical tool; threshold voltage; Design optimization; Fabrication; Integrated circuit modeling; Manufacturing processes; Process design; Response surface methodology; SPICE; Semiconductor device modeling; Threshold voltage; Time to market;
Conference_Titel :
Quality Electronic Design, 2001 International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1025-6
DOI :
10.1109/ISQED.2001.915269
