Title :
Memory hierarchy optimization of multimedia applications on programmable embedded cores
Author :
Tatas, K. ; Argyriou, A. ; Dasigenis, M. ; Soudris, D. ; Zervas, N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece
Abstract :
Data memory hierarchy optimization and partitioning for a widely used multimedia application kernel known as the hierarchical motion estimation algorithm is undertaken, with the use of global loop and data-reuse transformations for three different embedded processor architecture models. Exhaustive exploration of the obtained results clarifies the effect of the transformations on power, area, and performance and also indicates a relation between the complexity of the application and the power savings obtained by this strategy. Furthermore, the significant contribution of the instruction memory even after the application of performance optimizations to the total power budget becomes evident and a methodology is introduced in order to reduce this component
Keywords :
embedded systems; memory architecture; motion estimation; multimedia computing; data-reuse transformations; embedded processor architecture models; global loop; hierarchical motion estimation algorithm; memory hierarchy optimization; multimedia application kernel; multimedia applications; performance optimizations; power savings; programmable embedded cores; total power budget; Application software; Computer architecture; Embedded computing; Energy consumption; Memory; Motion estimation; Partitioning algorithms; Testing; Variable speed drives; Very large scale integration;
Conference_Titel :
Quality Electronic Design, 2001 International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-1025-6
DOI :
10.1109/ISQED.2001.915271
