A retargetable optimizing code generator for digital signal processors

Efficient DSP software synthesis for systems with stringent cost and power constraints requires tools which minimize code size as well as tools to evaluate processor architectures for a given application. In this paper, we introduce a user retargetable code generator translating homogeneous atomic data flow graphs into high-quality DSP assembly code. By using a target architecture description file, flexibility in the design process is enhanced without impairing final code quality. Based on a trellis tree straight-line code generation algorithm, we present a method for code compaction and register optimization to exploit instruction level parallelism. The results of our code generator match the quality of assembly programs which were coded by hand and thoroughly optimized