Exploitation of operation-level parallelism in a processor of the CRAY X-MP

Author

Vajapeyam, Sriram ; Sohi, Gurindar S. ; Hsu, Wei-Chung

Author_Institution

Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA

fYear

1990

fDate

17-19 Sep 1990

Firstpage

20

Lastpage

23

Abstract

Available operation-level parallelism and its exploitation in the CRAY X-MP processor are studied. Considered are the sizes and contributions to execution time of basic blocks, instruction and operation issue rates and issue stalls, and operation execution overlap for entire executions of three large programs, FLO52, TRFD, and QCD1, taken from the Perfect Club benchmark set. The large basic blocks account for a significant portion of the overall execution time. It is also found that with the use of vector instructions, the X-MP is able to issue more than one operation per clock cycle, even though it can issue a maximum of one instruction per cycle

Keywords

Cray computers; parallel machines; program compilers; scheduling; CRAY X-MP processor; FLO52; Perfect Club benchmark set; QCD1; TRFD; basic blocks; clock cycle; execution time; instruction issue rates; issue stalls; operation execution overlap; operation issue rates; operation-level parallelism; vector instructions; Application software; Clocks; Dynamic scheduling; Hardware; Parallel processing; Pipeline processing; Processor scheduling; Production; Program processors; Vector processors;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2079-X

Type

conf

DOI

10.1109/ICCD.1990.130149

Filename

130149