DocumentCode :
302202
Title :
A hierarchical multiprocessor scheduling system for DSP applications
Author :
Pino, JosC Luis ; Bhattacharyya, Shuvra S. ; Lee, Edward A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Volume :
1
fYear :
1995
fDate :
Oct. 30 1995-Nov. 1 1995
Firstpage :
122
Abstract :
This paper discusses a hierarchical scheduling framework which reduces the complexity of scheduling synchronous data flow (SDF) graphs onto multiple processors. The core of this framework is a clustering algorithm that decreases the number of nodes before expanding the SDF graph into a precedence directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. We have developed the SDF composition theorem for testing if a clustering step is valid. The advantages of this framework are demonstrated with several practical, real-time examples.
Keywords :
data flow computing; data flow graphs; directed graphs; parallel algorithms; processor scheduling; signal processing; DSP applications; SDF composition theorem; SDF graph; clustering algorithm; clustering step testing; directed acyclic graph; hierarchical multiprocessor scheduling system; memory usage; multiprocessor scheduler; synchronous data flow graphs; uniprocessor SDF schedulers; Application software; Clustering algorithms; Digital signal processing; Laboratories; Parallel processing; Processor scheduling; Runtime; Signal processing algorithms; Switches; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
ISSN :
1058-6393
Print_ISBN :
0-8186-7370-2
Type :
conf
DOI :
10.1109/ACSSC.1995.540525
Filename :
540525
Link To Document :
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