Synthesis of memories from behavioral HDLs

This paper describes anew approach for synthesizing small memories, such as multi-port register files, from behavioral HDLs. While such memories can be generated using conventional gate-level synthesis techniques, we present a method for extracting logic for a memory and then generating its design from one of three possible architectures. The techniques offer reductions in layout area and provide more compact HDL descriptions of designs by allowing behavioral descriptions instead of structural instantiations. In addition, the designer can experiment with multiple architectural implementations for the memory without changing the HDL description, and select the best architecture for the application