Automatic layout generation for mixed analog-digital VLSI neural chips

A systematic approach to automatic layout generation for the emerging mixed analog-digital VLSI neural systems is described. A macro-cell layout methodology based on a hierarchical floorplanning and placement procedure, a constraint-driven analog module generator, and a priority-based block router have been exclusively developed for neural chip implementation. Special analog VLSI layout constraints are analyzed and properly incorporated into the layout generation on each level of the circuit hierarchy to achieve both high performance and overall area efficiency. The floorplans for single-layer fully-connected Hopfield neural chips and multiple-layer neural chips have been developed. Experimental results on a 16-neuron neural circuit are presented