Exploring ASIC design space at system level with a neural network estimator

Author

Ellervee, Peeter ; Jantsch, Axel ; öberg, Johnny ; Hemani, Ahmed ; Tenhunen, Hannu

Author_Institution

KTH-Electron., R. Inst. of Technol., Kista, Sweden

fYear

1994

fDate

19-23 Sep 1994

Firstpage

67

Lastpage

70

Abstract

Estimators are critical tools in carrying out architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows the description of arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and present results of the first experiments made with realistic design examples

Keywords

application specific integrated circuits; circuit CAD; data flow graphs; estimation theory; integrated circuit design; multilayer perceptrons; ASIC design space; CAD; estimation function; multilayer perceptron; neural network estimator; system level; Application specific integrated circuits; Hardware; High level synthesis; Multi-layer neural network; Multilayer perceptrons; Network synthesis; Neural networks; Process design; Space exploration; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-2020-4

Type

conf

DOI

10.1109/ASIC.1994.404607

Filename

404607