DocumentCode
302270
Title
The star multiplier
Author
De Angel, Edwin ; Chowdhury, Andalib ; Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
1
fYear
1995
fDate
Oct. 30 1995-Nov. 1 1995
Firstpage
604
Abstract
This paper presents the architecture of a new high speed parallel multiplier. A novel architecture based on two ring structures and the modified-Booth (1951) algorithm achieve high speed multiplications with a significant reduction in hardware. The 32 by 32 bit star multiplier has been designed in a 0.6 /spl mu/m CMOS technology and presents a multiplication time of 17.5 ns.
Keywords
CMOS digital integrated circuits; VLSI; digital arithmetic; digital signal processing chips; multiplying circuits; parallel architectures; 0.6 micron; 17.5 ns; 32 bit; CMOS technology; DSP chips; VLSI chips; hardware reduction; high speed multiplications; high speed parallel multiplier architecture; modified-Booth algorithm; multiplication time; ring structures; star multiplier; Adders; CMOS technology; Circuits; Clocks; Computer architecture; Delay lines; Digital signal processing; Digital signal processing chips; Hardware; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-8186-7370-2
Type
conf
DOI
10.1109/ACSSC.1995.540619
Filename
540619
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