• DocumentCode
    302271
  • Title

    Evaluation of Booth´s algorithm for implementation in parallel multipliers

  • Author

    Bonatto, Pascal ; Oklobdzija, Vojin G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
  • Volume
    1
  • fYear
    1995
  • fDate
    Oct. 30 1995-Nov. 1 1995
  • Firstpage
    608
  • Abstract
    The Booth (1951) encoding technique, used in parallel multipliers seems to be obsolete because of the improvement of compression trees using 4:2 compressors. This article compares the two techniques in the case of different lengths of multipliers, and it appears that the reduction bit with 4:2 compressors allows a higher speed and a highly regular layout since the schematic is simple and repetitive.
  • Keywords
    digital arithmetic; digital signal processing chips; multiplying circuits; parallel algorithms; 4:2 compressors; Booth algorithm; Booth encoding technique; DSP; compression trees; floating point standard; parallel multipliers; reduction bit; regular layout; Compressors; Delay effects; Encoding; Noise generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 1995. 1995 Conference Record of the Twenty-Ninth Asilomar Conference on
  • Conference_Location
    Pacific Grove, CA, USA
  • ISSN
    1058-6393
  • Print_ISBN
    0-8186-7370-2
  • Type

    conf

  • DOI
    10.1109/ACSSC.1995.540620
  • Filename
    540620
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=302271