High-frequency sequential decimal multipliers

Multiplication, as one of the four basic operations embedded in arithmetic processors, is nowadays experiencing being spotlighted by the hardware designers involved in the revived decimal arithmetic. The decimal hardware units usually employ the sequential implementation for this operation, due to the high area cost of the parallel decimal multipliers. However, the main drawback of this iterative method is in regard to its high latency. This paper, with the intention of ameliorating this problem, proposes a high-frequency sequential decimal multiplier. The cycle time of the proposed multiplier is determined by a decimal carry-save adder which is about 22% less than that of the fastest previous design.