Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system

Author

Miura, Katsuyoshi ; Nakamae, Koji ; Fujioka, Hiromu

Author_Institution

Fac. of Eng., Osaka Univ., Japan

fYear

1997

fDate

28-31 Jan 1997

Firstpage

329

Lastpage

332

Abstract

A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remain unchanged that allow us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit in a consistent manner independently of circuit functions. The applied results of the CAD layouts of some sequential CMOS benchmark circuits show its superiority to the guided-probe method where circuit logical functions are first extracted from the CAD layout data and then the guided-probe testing is executed

Keywords

CMOS logic circuits; VLSI; circuit layout CAD; combinational circuits; electron beam testing; fault diagnosis; integrated circuit design; logic CAD; logic testing; sequential circuits; transistor circuits; CAD layout; CAD-linked EB test system; CAD-linked electron beam test system; VLSI sequential circuits; circuit logical functions; combinational circuits; guided-probe method; hierarchical fault tracing; lowest primitive cell; sequential CMOS benchmark circuits; top level cell; transistor-level circuit; Benchmark testing; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Electron beams; Sequential analysis; Sequential circuits; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

Conference_Location

Chiba

Print_ISBN

0-7803-3662-3

Type

conf

DOI

10.1109/ASPDAC.1997.600173

Filename

600173