Design for cold test elimination - facing the Inverse Temperature Dependence (ITD) challenge

Historically, circuits that operate in a high-temperature region could cause an increase in the total delay (td) especially in the process technology prior to the 90nm node. This was because both interconnects and transistors were slowing down as the temperature rose. However, for transistors with the 90nm process technology and beyond, this phenomena has started to change. In particular, the threshold voltage, V_t, to supply voltage, VCC, ratio of high-V_t cells in a library is now very close to 1. As a result, the consequence of this event is called an Inverted Temperature Dependence (ITD) effect. There are two key parameters that determine the transistor temperature behavior. They are the mobility, μ, and the threshold voltage, V_t. Both decrease with an increasing temperature. This new, complicated dependence of delay vs. temperature poses new challenges to circuit designers. This paper describes the physics behind the ITD effect on the design of modern, nanometer VLSI circuits. We also provide a case study that demonstrates a new ITD effect compensation feature. This new design approach will produce an outgoing level of quality that minimizes the risk of eliminating the cold test elimination (CTE) in the manufacturing. The elimination of cold test will help improving manufacturing capacity for optimized cycle time and product delivery. Hence, this new ITD design breakthrough has been proliferated to the recent process technology nodes.