Title :
A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS
Author :
Hu, Shijie ; Jia, Chen ; Huang, Ke ; Zhang, Chun ; Zheng, Xuqiang ; Wang, Zhihua
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average phase error. The power consumption is 15mW for 1V supply.
Keywords :
CMOS logic circuits; receivers; CMOS technology; PI-based CDR logic circuit; bit rate 10 Gbit/s; clock and data recovery circuit; half-rate clock; phase detector; phase interpolator; phase selector; power 15 mW; power consumption; sample unit; size 65 nm; source synchronous receiver; synchronize unit; voltage 1 V; Bandwidth; CMOS integrated circuits; Clocks; Computer architecture; Jitter; Simulation; Synchronization;
Conference_Titel :
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-4673-0218-0
DOI :
10.1109/ISCAS.2012.6271973
