Title :
Constant delay logic technology
Author :
Hall, David W. ; Dooley, J.G. ; Hernandez, Arecio A.
Author_Institution :
Gov. Aerosp. Syst. Div., Harris Corp., Melbourne, FL, USA
Abstract :
The design of a digital IC is complicated by the range of timing that must be considered in the design process. Delay variations are commonly associated with power supply variations, temperature and process parameter variations. This paper documents one approach to reducing the delay variations, resulting from environmental conditions and process parameter variations, encountered in digital logic to levels approaching insignificance. This approach does not impact the delay dependency on output loading
Keywords :
delays; field effect logic circuits; integrated circuit noise; timing; constant delay logic technology; delay variations; digital logic; environmental conditions; output loading; process parameter variations; timing range; Application specific integrated circuits; Delay; Government; Inductance; Integrated circuit noise; Logic devices; Noise reduction; Semiconductor device noise; Variable structure systems; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-2020-4
DOI :
10.1109/ASIC.1994.404611
