Simulating clock jitter in digital communication systems

Several digital communication systems in current use operate on analog channels. We address the issues involved in simulating the non-ideal behavior of sampling clocks in such systems in the time domain. Conventionally, this issue has either been ignored or dealt with inefficiently and/or inaccurately. We present a technique that allows efficient simulation of sampling clock jitter without compromising accuracy. Our approach is based on recognizing that any digital communication system may be naturally partitioned into digital and analog parts separated by analog to digital and digital to analog convertors. By simulating the convertors in a non-traditional manner, it is possible to reliably model clock jitter without adding significant overhead and entirely avoiding oversampling. We detail this methodology for the simulation of clock jitter in digital communication systems and specify a software architecture for its implementation. We also provide an illustration of this methodology applied to simulating a real-world communication system