Title :
Design, verification, and test of a true single-phase 8-bit adiabatic multiplier
Author :
Kim, Suhwan ; Ziesler, Conrad H. ; Papaefthymiou, Marios C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Abstract :
In this paper we present the design and experimental evaluation of an an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generator: Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitary of 91 pJ per multiplication at 100 MHz. The chip has been fabricated in a 0.5 μm standard CMOS process with an active area of 0.47 mm2. Correct chip operation has been validated for operating frequencies up to 130 MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions
Keywords :
CMOS logic circuits; SPICE; built-in self test; logic CAD; logic simulation; logic testing; multiplying circuits; 0.5 micron; 100 to 130 MHz; 8 bit; HSPICE simulations; SCAL-D; active area; built-in self-test; identical biasing conditions; operating frequencies; post-layout extracted parasitics; single-phase adiabatic multiplier; single-phase sinusoidal power-clock generator; standard CMOS process; Built-in self-test; Capacitance; Circuit simulation; Clocks; Design optimization; Energy efficiency; Frequency; Logic design; Logic testing; Power generation;
Conference_Titel :
Advanced Research in VLSI, 2001. ARVLSI 2001. Proceedings. 2001 Conference on
Conference_Location :
Salt Lake City, UT
Print_ISBN :
0-7695-1038-8
DOI :
10.1109/ARVLSI.2001.915549
