A 1-MHz and 16-bit ΣΔ DAC with a 224th-order reconstruction FIR-filter using only 9 nonzero taps

This paper presents a 65-MHz clock rate and 32-times oversampling digital-to-analog sigma-delta converter in a standard 1 μm CMOS technology. The modulator have been designed for large bandwidth, large input range and low tonality. These demands have been met by a 6th-order lossy modulator. To utilize the modulator bandwidth and relax the reconstruction filter requirements a high-order FIR-filter have been used that combines D/A-conversion with a sharp transition-band filtering. For the application novel use of a interpolated half-band FIR-filter gives a low number of nonzero tap coefficients compared to earlier reported designs