Substrate noise suppression technique for power integrity of TSV 3D integration

Author

Po-Jen Yang ; Po-Tsang Huang ; Wei Hwang

Author_Institution

Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

20-23 May 2012

Firstpage

3274

Lastpage

3277

Abstract

In this paper, a substrate noise suppression technique is proposed for the power integrity of TSV 3D integrations. This substrate noise suppression technique reduces both substrate and TSV coupling noises using active substrate decouplers (ASDs) to absorb the substrate noise current. Additionally, the ASD placing is also presented to suppress noises effectively for different 3D structures. For a processor-memory stacking integration, the ground bouncing noises can be reduced by 44.1% via the noise suppression technique. The proposed substrate noise suppression technique can enhance the power integrity of TSV 3D-ICs by reducing the coupling substrate noises.

Keywords

integrated circuit noise; power integrated circuits; three-dimensional integrated circuits; ASD; TSV 3D integration; TSV coupling noises; active substrate decouplers; power integrity; substrate noise suppression technique; Analog circuits; Couplings; Noise; Random access memory; Substrates; Through-silicon vias; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2012 IEEE International Symposium on

Conference_Location

Seoul

ISSN

0271-4302

Print_ISBN

978-1-4673-0218-0

Type

conf

DOI

10.1109/ISCAS.2012.6272024

Filename

6272024