Thermal aware timing budget for buffer insertion in early stage of physical design

Thermal generation by power dissipation of the highly integrated System on Chip (SoC) device is irregularly distributed on the intra chip. It leads to thermal increment of the each thermally different region and effects on the propagation timing; consequently, the timing violation occurs due to the misestimated number of buffers. In this paper, the timing budgeting methodology which contains the estimated thermal distribution on a chip in the early stage of physical design by modeled the RC delay considering temperature and buffer insertion planning using by the proposed delay model are presented. Simulation results showed the reduction of the worst delay after buffer insertion up to 30% in contrast to the buffer insertion without considering temperature.