DocumentCode
3024970
Title
Low-cost, low-power and high-throughput BCH decoder for NAND Flash Memory
Author
Lee, Kijun ; Lim, Sejin ; Kim, Jaehong
Author_Institution
Memory Div., Samsung Electron., Hwasung, South Korea
fYear
2012
fDate
20-23 May 2012
Firstpage
413
Lastpage
415
Abstract
The BCH codes are widely used as Error Correcting Code (ECC) schemes for NAND Flash Memories. There have been strong demands to implement NAND Flash controller having low cost, low power and high throughput. We focus on BCH implementation since it has the largest portion in the controller. In this paper, we configure the 3-stage pipelined BCH decoder: syndrome computation, Berlekamp-Massey algorithm and Chien search. We implement BCH decoder supporting 800MB/s using the pipelined structure and the early termination method.
Keywords
BCH codes; NAND circuits; error correction codes; flash memories; 3-stage pipelined BCH decoder; BCH code; Berlekamp-Massey algorithm; Chien search; ECC scheme; NAND flash controller; NAND flash memory; early termination method; error correcting code scheme; pipelined structure; syndrome computation; Decoding; Error correction codes; Flash memory; Galois fields; Logic gates; Polynomials; Power dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2012 IEEE International Symposium on
Conference_Location
Seoul
ISSN
0271-4302
Print_ISBN
978-1-4673-0218-0
Type
conf
DOI
10.1109/ISCAS.2012.6272051
Filename
6272051
Link To Document