Improved hard-decision decoding LDPC Codec IP design

This paper presents an area efficient low density parity check (LDPC) encoder/decoder (Codec) implementation which can deliver high throughput performance and error correction capability for flash memory controller. In order to reduce the size of memory to store variable node LLR values, flooding schedule with column-by-column decoding architecture is exploited for the decoder. The encoder architecture provides area efficient encoding by using the specially designed H-matrix structure. The LDPC Codec IP is implemented with 700Kgates of 45nm standard CMOS technology of Samsung ASIC library and can support decoding data of 400MB/s from NAND flash without compromising the error correction capability up to raw bit-error-rate (BER) range of 2.5E-3 by hard-decision decoding mode.