Novel integration technologies for improving reliability in NAND flash memory

NAND flash has been scaled down intensively to 2Y nm generation to satisfy the increasing demand for high-density memories. However, as technology node advances, various scaling barriers newly appeared and reliability characteristics of NAND flash such as endurance and data retention deteriorated. Maximum Vth of a programmed cell becomes lower with scaling down, resulting in insufficient program window for MLC operation. Floating gate (FG) and inter-poly dielectric (IPD) structure must be carefully optimized to maximize saturated level of programmed Vth. The tight control of Vth distribution is one of the main issues in scaling for reliability margin. By decreasing depletion in floating gate and control gate (CG), widening of cell Vth distribution width can be efficiently suppressed. The effect of traps in gate oxide to reliability increases with the decrease in cell dimension. To lower interface trap of gate oxide, hydrogen reducing back-end-of line (BEOL) process is introduced. By using new BEOL process, endurance and data retention characteristics are drastically enhanced. In this paper, we will present the major scaling issues and integration technologies for improving reliability in NAND flash memory for 2Ynm generation and beyond.