Design of Low Power Mixed Radix FFT Processor for MIMO OFDM Systems

In this paper the design of 128/64 point Fast Fourier transform processor (FFT Processor) is proposed to support future generation Multiple- Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO -OFDM) based IEEE 802.11n wireless local area network base band processor. The pipelined mixed radix multipath delay feedback (MRMDF) FFT architecture is proposed to provide as higher throughput rate combining the characteristics of both Single path Delay Feedback (SDF) which is used to reduce memory size and Multipath Delay feedback (MDF) by using the multidata-path scheme. The proposed processor not only supports the operation of FFT in 128 point and 64 point but can also provide different throughput rates for 1-4 simultaneous data sequence to meet IEEE 802.11n requirements. Further less hardware complexity is needed in this deign compared with traditional four parallel approach. The mixed radix FFT algorithm will also reduce the power consumption. The proposed FFT Processor is implemented VHDL and the simulation results are presented.