Scalable multistage networks for multiprocessor system-on-chip design

This paper presents a micro-network that is a generic, scalable and multi-stage interconnect architecture for systems on chip (SoC). The network architecture relies on packet switching and point-to-point bi-directional links between the routers implementing the micro-network. The NoC provides a configurable number of OCP compliant communication interfaces for both initiators (masters) and targets (slaves). This network has been used in a multiprocessor SoC with 16 initiators and 16 slaves, and compared with an AMBA bus in terms of latency and saturation threshold.